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Name |
MANEUX (M.Sc., PhD) |
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First name |
Cristell |
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Birth date |
12-Jun-1968 |
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Function |
Electronics engineer, Researcher |
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Position/Rank |
Professor, Team Leader |
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Professional address |
Université de Bordeaux |
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Phone number |
(33) 5 4000 2858 |
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e-mail address |
cristell.maneux @ u-bordeaux.fr |
UNIVERSITY DEGREES AND QUALIFICATIONS
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Since 09/2012 |
Full Professor, IMS Laboratory, Department of Sciences and Engineering, University of Bordeaux, France. |
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01/2008-01/2022 |
Head of the Electrical Characterization and Compact Modeling Team, IMS Laboratory, University of Bordeaux |
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10/2007 |
Accreditation to conduct researches, University of Bordeaux, France. |
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09/1998-09/2012 |
Associate Professor, IMS Laboratory, Department of Sciences and Engineering, University of Bordeaux, France. |
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09/1997-09/1998 |
Lecturer and Research Assistant, University of Bordeaux, France. |
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01/1998 |
Ph.D. degree in electronics, University of Bordeaux, France. |
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09/1995-09/1997 |
Peer-tutoring, University of Bordeaux, France. |
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06/1994 |
M.Sc. degree in Electronics engineering, University of Bordeaux, France. |
LOCAL, NATIONAL and INTERNATIONAL MAIN RESEARCH RESPONSABILITIES
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Since 01/2022 |
Director of IMS Lab, University of Bordeaux, Bordeaux INP, CNRS. |
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Since 01/2017 |
Deputy Director of GDR SoC2 (System On Chip, Systèmes embarqués et Objets Connectés) gathering researchers from 39 CNRS laboratories (INS2I and INSIS). |
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01/2016 – 01/2022 |
Deputy Director of IMS Lab, University of Bordeaux, Bordeaux INP, CNRS. |
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April 2016 |
Delegate CEFIPRA, Bangalore, India. |
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Feb. 2014 |
Delegate Carleton University, Canada. |
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2014-2018 |
Elected member of the University of Bordeaux research council. |
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2013-2016 |
Ph. D. International joint supervision with the University of Naples, Italy. |
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Since 2012 |
Member of the ’’Embedded Systems’’ strategic council of Competitiveness Cluster for Aeronautics, Space and Embedded Systems (Aerospace Valley). |
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2012-2016 |
Member of the board of Axe 3 CPU cluster “Excellence Initiative IDEX Bordeaux”. |
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2012-2018 |
Chairwoman of the URSI FRANCE commission D. |
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Since 2012 |
Track Modelling member of the Technical program committee of the European Solid-State Device Research Conference. |
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2010-2018 |
Member of the national ’’Observatoire Micro/Nanotechnologies’’. |
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2009-2011 |
Member of the national research evaluation committee of ANR P3N. |
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Since 2008 |
Member of the GDR SiP-SoC steering committee. |
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2008-2011 |
Elected member of the Bordeaux 1 University research council. |
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2007-2011 |
Elected member of the research council of IMS Lab. |
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Since 2006 |
Member of the steering committee of the IMS-ST Microelectronics common lab. |
RESEARCH MAIN ACHIEVEMENTS
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From 2008 to 2022, I was leading the “MODEL” team and has 20 years’ experience in advanced and emerging device modelling including the world-wide-used and the success story of the Carbon Nanotube based transistor models.
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I was the leader of the former ANR ROBUST project (2009-2012) which was an ambitious industrial research project focused on advanced technological activities to provide robust ICs designs for emerging 100G Ethernet.
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I was leading the project ULTIMATE (2016-2021), a five-year international ambitious project focused on upper limit InP-based technology investigations mandatory to attain THz electronics. The ULTIMATE project tackles the design of ultrahigh-speed transistors on a fundamental atomistic level, with Density-Functional Theory (DFT) for accurate band structure calculations and quantum transport simulations to break through the present bandwidth bottleneck and finally experimentally achieve 750-1000 GHz cutoff frequencies. http://ultimate.cnrs.fr/
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I was leading the French ANR LEGO (2018-2022) project which is intended to fill the gap between device research and the innovative logic circuit implementation through the following objectives:
– demonstrate the proof of concept of stacked vertical NWFET for non-conventional logic circuit,
– develop a design kit including compact models to support the circuit design flow
– prove enhanced logic functionality and logic circuit operation in terms of propagation delay, dynamic and static power consumption, resilience to temperature and supply voltage variation assess the technology roadmap improvements and the associated logic performance metrics. http://lego.cnrs.fr/
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Currently, I’m leading the Programme H2020 FET PROACT FVLLMONTI (2021-2025) , “Ferroelectric Vertical Low energy, Low latency, low volumes Modules fOr Neural network Transformers In 3D”. Through actual Vertical NanoWaire Field Effect Transistr, VNWFET fabrication setting up a design-technology co-optimization (DTCO) approach, the FVLLMONTI vision is to develop regular 3D stacked hardware layers of NNs empowering the most efficient machine translation thanks to fine-grain hardware / software co-optimisation. http://www.fvllmonti.eu/
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Since May 2024, I coordinate the “Ferro Futures” action for the PEPR ELECTRONIQUE. The aim is to demonstrate all the scientific and technological elements necessary to set up the value chain of a future French Ferroelectronics Sector that meets the specific needs of Embedded Artificial Intelligence (IAe). http://www.pepr-electronique.fr/fer/
MAIN AREA OF INTEREST
- Compact modelling of advanced and emerging devices: InP HBT, SiGe HBT, Carbon NanoTube Transistors, Graphene Transistors, Nanowire Transistors;
- Device electrical characterization: DC, RF, pulsed, Low Frequency noise, Random Telegraph Noise;
- Device failure mechanisms, Integrated circuit reliability;
- THz transmissions for Beyond 5G communications.
PUBLICATIONS and SUPERVISIONS
- 82 International journal publications referenced in IEEE Transaction on Electron Device, IEEE Transaction Circuits and Systems, IEEE Electron Device Letters, IEEE Transaction on Material and Reliability, IEEE Proceedings, Proceedings of the National Academy of Sciences, …
- 141 International conference publications in the ESSDERC, ESREF, EUMW, …
- 24 Ph.D Thesis supervisions including 5 industrial CIFRE
- 13 post-docs supervisions (representing 13 cumulative years)
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